1. Field of the Invention
The present invention relates generally to package structures, and more particularly, to a high-quality and low-cost package structure.
2. Description of Related Art
In a conventional lead frame based semiconductor package, such as a QFN (Quad Flat Non-lead) package, a semiconductor chip is adhered to a chip carrier, such as a lead frame, and encapsulated by an encapsulant, and leads of the lead frame are exposed from the encapsulant to serve as I/O connections for electrically connecting the semiconductor chip to an external device, such as a printed circuit board, as disclosed by U.S. Pat. No. 5,942,794, No. 6,143,981, No. 6,229,200 and No. 6,498,099.
In addition, carrier-free packages are developed to reduce package size, as disclosed by U.S. Pat. No. 5,830,800 and No. 6,770,959. FIGS. 1A to 1C show such a carrier-free package. Referring to FIG. 1A, a metal plate 10 made of copper is prepared, and a plurality of electrical contact pads 11 is formed on the metal plate 10 by electroplating. Referring to FIG. 1B, a chip 12 is adhered to the metal plate 10 and electrically connected to the electrical contact pads 11 through bonding wires 13. Then, an encapsulant 14 is formed on the metal plate 10 to cover the chip 12 and the bonding wires 13. Referring to FIG. 1C, the metal plate 10 is removed by etching such that the bottom surfaces of the electrical contact pads 11 are exposed to serve as I/o connections for electrically connecting to an external device.
However, with the metal plate 10 being unfit for routing, lengthy bonding wires are required, thereby increasing the cost and adversely affecting the electrical performance of the package.
Accordingly, U.S. Pat. No. 6,884,652 discloses a carrier-free package that can arrange conductive traces and shorten bonding wires so as to improve the electrical performance of the package. FIGS. 1A′ to 1C′ show such a carrier-free package. Referring to FIG. 1A′, a metal plate 10 made of copper is prepared, and a dielectric layer 100 is formed on the metal plate 10 to allow a plurality of openings to be formed in the dielectric layer 100 to expose portions of the metal plate 10. Referring to FIG. 1B′, a wiring layer 11′ is formed on the dielectric layer 100 by such as sputtering. The wiring layer 11′ comprises a plurality of conductive traces 111, a plurality of electrical contact pads 112 and bond fingers 113 formed at two ends of the conductive traces 111, respectively. Then, a chip 12 is adhered over the dielectric layer 100 and electrically connected to the bond fingers 113 through bonding wires 13. Then, referring to FIG. 1C′, an encapsulant 14 is formed over the dielectric layer 100 to cover the wiring layer 11′, the chip 12 and the bonding wires 13, and a singulation process is performed. Thereafter, the metal plate 10 is removed by such as etching to expose the bottom surfaces of the electrical contact pads 112. The exposed bottom surfaces of electrical contact pads 112 serve as I/o connections for electrically connecting to an external device.
However, the above-described technique incurs high costs and requires complicated processes and is not suitable for mass production because of the necessity of forming the dielectric layer 100 on the metal plate 10 and forming the wiring layer 11′ by such as sputtering.
Accordingly, a semiconductor package that can arrange conductive traces but dispense with a dielectric layer is proposed by U.S. Pat. No. 6,306,682. FIGS. 1A″ to 1D″ show the semiconductor package.
Referring to FIG. 1A″, a metal plate 10 made of copper and having a first surface 10a and an opposed second surface 10b is prepared, an electroplated metal layer 101 and an electroplated wiring layer 11′ are formed on the first surface 10a and the opposed second surface 10b of the metal plate 10, respectively. The wiring layer 11′ comprises a plurality of electrical contact pads 112. A solder mask layer 15 is further formed on the second surface 10b and the wiring layer 11′. A plurality of openings 150 is formed in the solder mask layer 15 to expose the bottom surfaces of the electrical contact pads 112. The exposed bottom surfaces of the electrical contact pads 112 serve as I/o connections for electrically connecting to an external device. Referring to FIG. 1B′, the metal plate 10 is etched, from the first surface 10a of the metal plate 10, to form an open area 101a which penetrates the metal plate 10. As shown in FIG. 1C″, a chip 12 is received in the open area 101a such that the chip 12 is adhered to the solder mask layer 15 and electrically connected to the electrical contact pads 112 through bonding wires 13. Further, an encapsulant 14 is formed in the open area 101a to encapsulate the chip 12 and the bonding wires 13, and solder balls 16 are formed on the electrical contact pads 112 in the openings 150. Finally, as shown in FIG. 1D″, the package is singulated along the periphery of the open area 101a so as to remove the metal plate 10.
However, in the above-described technique, due to the material characteristics of the solder mask layer 15, it is difficult to form an even surface on the solder mask layer 15. As such, when the chip 12 is adhered to the solder mask layer 15, a crack S can easily occur to the solder mask layer 15 (as shown in FIGS. 1C″ and 1D″), thus reducing the product yield. Further, since lithography processes such as mask and exposure processes are required for forming the openings 150 in the solder mask layer 15, it incurs high costs and precludes mass production.
Therefore, it is imperative to overcome the above drawbacks of the prior art.